Generally, semiconductor integrated circuit devices are tested to determine whether they have been manufactured to have electric properties satisfying a design standard, and test equipment thereof is probe equipment. A probe card, as an element of the probe equipment, is designed to come into contact with a pad provided in a semi-conductor integrated circuit device, thereby serving to electrically communicate various electric signal generators or signal detectors of the probe equipment with the pad. Through the electric communication between probes on the probe card and the pad, it is tested whether the semiconductor integrated circuit device operates normally or not.
Conventionally, a cantilever-type probe card has a 4×8 chip array structure (32 DUT in parallel) to correspond to a chip array of an electronic component being tested.
Referring to FIGS. 1 to 3, a manufacturing process of the conventional normal probe card is illustrated in plan views.
Explaining the manufacturing process of the conventional probe card in brief, first, as shown in FIG. 1, bumps 11 are formed at a surface of a probe substrate 10 to correspond to pads arranged on a surface of an electronic component, chip, etc. being tested.
Then, as shown in FIG. 2, a 6-inch silicon wafer 20, having probe tips 21 and supporting beams 22 formed at a surface thereof, is prepared. Here, the bumps 11, probe tips 21, and supporting beams 22 are formed by photolithography and plating processes.
After preparing the probe substrate 10 and the silicon wafer 20, as shown in FIG. 3, a solder paste P is applied to an upper end of each bump 11. In succession, the silicon wafer 20 is placed on the probe substrate 10 so that an end of each supporting beam 22 comes into contact with the upper end of each bump 11, and is heated to a temperature of approximately 200 to 350 degree Celsius. Thereby, the bump 11 and the supporting beam 22 are attached to each other as the solder paste P is molten. Finally, by removing the silicon wafer 20 via etching, a probe bonding process, that is a key process in the manufacture of a probe card, is completed.
Nowadays, in tandem with development of semiconductor manufacture techniques, an increased number of chips are formed on a single substrate to reduce manufacturing costs and improve productivity. This consequently results in scale-up of a probe card used to test the chips.
FIGS. 4 to 6 are plan views illustrating a manufacturing process of a conventional large-scale probe card.
As shown in FIGS. 4 to 6, a large-scale probe substrate 30 having a 8×16 chip array structure (128 DUT in parallel) and a 12-inch silicon wafer 40 to correspond to the large-scale probe substrate 30 are used to manufacture the conventional large-scale probe card.